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As advances in technology and circuit design increase working frequencies of microprocessors, DSPs and different quick chips, new design challenges proceed to emerge. One of many main efficiency limitations in at present's chip designs is clock skew, the uncertainty in arrival occasions between a pair of clocks. Growing clock frequencies are forcing many engineers to rethink their timing budgets and to make use of skew-tolerant circuit methods for each domino and static circuits. Whereas senior designers have long developed their very own methods for decreasing the sequencing overhead of domino circuits, this data has routinely been protected as commerce secret and has not often been shared. Skew-Tolerant Circuit Design presents a scientific approach of attaining the identical aim and places it in the arms of all designers.
This book clearly presents skew-tolerant methods and exhibits how they address the challenges of clocking, latching, and clock skew. It supplies the training circuit designer with a clearly detailed tutorial and an insightful abstract of the newest literature on these crucial clock skew points.
* Synthesizes the newest advances in skew-tolerant design in one cohesive tutorial
* Supplies incisive instruction and recommendation punctuated by humorous illustrations
* Consists of workouts to check understanding of key ideas and options to chose workouts
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