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Formal Equivalence Checking and Design Debugging (Frontiers in Electronic Testing) Pdf

Download Formal Equivalence Checking and Design Debugging (Frontiers in Electronic Testing) Pdf

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Book Description:

Formal Equivalence Checking and Design Debugging covers two primary topics in design verification: logic equivalence checking and design debugging. The first part of the book critiques the design points that require logic equivalence checking and describes the underlying utilized sciences that are used to unravel them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations similar to retiming are described in factor.
The second part of the book offers a radical survey of earlier and present literature on design error evaluation and design error correction. This half moreover provides an in-depth analysis of the algorithms used in two logic debugging software packages, ErrorTracer and AutoFix, developed by the authors.
From the Foreword:
`With the adoption of the static sign-off technique to verifying circuit implementations the equipment-specific constructed-in circuit (ASIC) business will experience the first radical methodological revolution as a result of the adoption of logic synthesis. Equivalence checking is among the many two important elements of this methodological revolution. This book is nicely timed for each the designer in search of to raised understand the mechanics of equivalence checking or for the CAD researcher who must analysis properly-motivated evaluation points resembling equivalence checking of retimed designs or error evaluation in sequential circuits.'
Kurt Keutzer, School of California, Berkeley




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